Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing

Data-parallel problems demand ever growing floating-point (FP) operations per second under tight area- and energy-efficiency constraints. In this work, we present Manticore, a general-purpose, ultraefficient chiplet-based architecture for data-parallel FP workloads. We have manufactured prototype of the chiplet’s computational core in Globalfoundries 22FDX process demonstrate more than 5x improvement energy efficiency on intensive workloads compared to CPUs GPUs. The compute capability at high area is provided “Snitch: A tiny pseudo dual-issue processor efficient execution workloads,” IEEE Trans. Comput., containing eight small integer cores, each controlling large unit (FPU). supports two custom ISA extensions: SSRs extension elides explicit load store instructions by encoding them as register reads writes (“Stream semantic registers: lightweight RISC-V achieving full utilization single-issue cores,” Comput.). repetition decouples from FPU allowing be issued independently. These extensions allow minimize its instruction fetch bandwidth saturate FPU, above 90%, with 40% dedicated FPU.